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`timescale 1 ps / 1 ps
module lvds_tx (
		input  wire       tx_inclock,   //   tx_inclock.tx_inclock
		output wire       tx_outclock,  //  tx_outclock.tx_outclock
		output wire       tx_coreclock, // tx_coreclock.tx_coreclock
		input  wire       pll_areset,   //   pll_areset.pll_areset
		output wire       tx_locked,    //    tx_locked.tx_locked
		input  wire [9:0] tx_in,        //        tx_in.tx_in
		output wire [0:0] tx_out        //       tx_out.tx_out
	);

	altera_soft_lvds_tx_OX0kT lvds_tx_inst (
		.tx_inclock   (tx_inclock),   //   tx_inclock.tx_inclock
		.tx_outclock  (tx_outclock),  //  tx_outclock.tx_outclock
		.tx_coreclock (tx_coreclock), // tx_coreclock.tx_coreclock
		.pll_areset   (pll_areset),   //   pll_areset.pll_areset
		.tx_locked    (tx_locked),    //    tx_locked.tx_locked
		.tx_in        (tx_in),        //        tx_in.tx_in
		.tx_out       (tx_out)        //       tx_out.tx_out
	);

endmodule
